It’s been clear for many years that three-dimensional NAND die stacking, during which chip layers are destined vertically as opposition horizontal tabular structures was the manner forward for next-generation chip styles. Until now, Samsung has been the sole company to require that plunge, however that’s getting to modification in 2015 with the launch of Intel’s own answer in 2015.
According to Intel, its 256-gigabit MLC NAND chips can encompass thirty two layers, and can even be on the market in a very 384-gigabit tending configuration. Intel is saying that its own 256 Gb die sets potency records, however as Anandtech reports, this relies on however you count — Samsung has consciously chosen to use a 32-layer 86Gbit die to attenuate its die foot print, as opposition maximizing capability. This provides Samsung’s V-NAND the littlest die size of any product presently on the market, with size being a really necessary considers several markets.
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